1. Technical Field of the Invention
The embodiments of the invention relate to testing methodology and, more particularly, to test signals crossing clock domains.
2. Description of Related Art
When an integrated circuit (IC) is manufactured, the IC chip undergoes a variety of testing to validate the design of the chip. For complex silicon chips, silicon debugging is one of the more difficult of system designs, due to inherent lack of visibility into the design state. In order to facilitate the performing of the debug procedures, various test and debug structures are designed into the IC. These test and debug structures are then accessed during a debug phase when testing the IC.
Although many such test and debug structures may be present in a chip, most are designed to address debugging within a single clock domain. For logic signals that traverse clock domains, single domain test structures may not allow for the debugging of designs and functionality of synchronizing circuits that are used to control the signal traversal from one clock domain to another clock domain. Since multiple layers of logic complexity may be designed on top of some synchronizing circuits, debugging and testing of synchronizing logic circuitry is difficult to achieve when debug procedures are limited to looking at signals in a single clock domain.
Furthermore, synchronization logic circuits are generally not testable directly through software. During functional testing, it is not possible to determine directly as a part of the functional test, whether a logic state traversal occurs properly across the clock domains bridged by the synchronizing circuit. In some ICs, scannable registers are employed to scan in and scan out a signal, but theses scan-ins and scan-outs are obtained through Joint Test Action Group (JTAG) scanning tools and then checked for consistency. However, such scan techniques do not offer a fine enough granularity at a logic level of the synchronizing circuit to determine if exactly one traversal occurred consistently. This is especially true when the latency across the synchronization point varies due to the clock ratio relationships across the clock domains.
Accordingly, it would be advantageous to have a test methodology that assesses the synchronization logic that controls clock domain crossings, as well as to provide a flexible way of repeating the test across the clock domains as the setup changes, when clock ratio relationship across the synchronizing circuit also change.